In this paper a low power Asynchronous FPGA is designed. Power gating technique is used in this paper which reduces power. The type of Power Gating used is Fine Grain Power Gating. In fine grain power gating, each LUT has its own sleep transistor and related sleep controller, so when any LUTs are inactive, they can be set to sleep mode immediately. LEDR encoding is done at input and output, which also reduces power. The circuit is simulated using Xilinx tool. Power reduction is achieved by selectively setting the functional units into a low leakage mode when they are inactive.