In this paper a new digit serial finite field multiplier using normal basis is proposed. In digit serial architecture data words with length m are partitioned into digits of few bits each and then processed on a digit by digit basis. If the digit size is L-bits and N=m/L the digit serial system process input data at a rate of L-bits per clock cycle and output is produced in every N clock cycle. Latency of a digit serial operation is the time taken to produce a digit. Using a sum of partial multiplication the latency is less compared with other digit serial multipliers. This architecture is well suitable for VLSI implementation and widely used in cryptographic application like elliptic curve cryptography.