Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 Print ISSN: 2250-1088 Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

Special Issue

Volume
  

Single Phase Seven Level Stand Alone Inverter for Photovoltaic System

Authors N. Shanmugavadivu and T. Annamalai

Keywords Multilevel inverter (MLI), Photovoltaic (PV) System, Pulse-Width Modulated (PWM), Total Harmonic Distortion (THD)

Pages 49-53

Small Delay Defect Detection Using Signature Register

Authors R. Mohanasundaram and E.K. Kavithaashri

Keywords Very Large Scale Integration (VLSI), Large Scale Integration (LSI), Design for Testability (DFT)

Pages 60-67

A Low Power Asynchronous FPGA with Power Gating and LEDR Encoding

Authors K. Naveena and N. Kirthika

Keywords In this paper a low power Asynchronous FPGA is designed. Power gating technique is used in this paper which reduces power. The type of Power Gating used is Fine Grain Power Gating. In fine grain power gating, each LUT has its own sleep transistor and rela

Pages 68-72

Secure Cryptosystem for Image Encryption & Decryption

Authors P. Geetha and S. Govindaraju

Keywords Chaos, Bb Equation, Pseudorandom Sequence, LFSR

Pages 73-78

VLSI Implementation of a 2x2 MIMO-OFDM System on FPGA

Authors R. Premalatha and M. Shanthi

Keywords MIMO-OFDM, FFT/IFFT, Channel Estimation, FPGA

Pages 79-84

Survey on VLSI Architecture for 2D DWT Using Lifting Scheme

Authors G.S. Ragavi and V. Geetha

Keywords Architecture, Discrete Wavelet Transform, Lifting, VLSI

Pages 85-89

A High Bit Rate Serial-Serial Multiplier

Authors K.R. Jisha and Dr.Rajeswari Mariappan

Keywords Serial Serial Multiplier, Asynchronous Counters, Serial Serial Algorithm

Pages 90-94

Comparative Analysis of Different Multiply Accumulate Architecture

Authors P.M. Sneha Angeline and M. Shanthi

Keywords Baugh Wooley, Critical Path Delay, Energy Per Operation

Pages 95-99

Performance Analysis of High Performance Adder Architectures

Authors Dr.P.T. Vanathi, Dr.J. Ramesh, K. Revathy, R. Preethi, C. Haritha Laxmi and K. Keerthana

Keywords 28T CMOS Adder, 10T SERF Adder,10T CLRCL Adder, 14T Full Adder ,Proposed 14T Full Adder, Power Consumption

Pages 100-104

Efficient Design of a Hybrid Adder Using Quantum-Dot Cellular Automata

Authors P. Vijayalakshmi and N. Kirthika

Keywords Hybrid Adder, QCA-Quantum-Dot Cellular Automat, Nano Electronics

Pages 105-109

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