Special Issue
Comparative Analysis of Fault Coverage Methods
Authors K.P. Keerthana and K. Kavitha
Keywords Fault Coverage, Hazard Based Detection, Broadside Test, Functional Broadside Test
Pages 110-113
Design of Low Power 8T SRAM Array with Improved Noise Margin
Authors K. Anbarasi, S. Chithra and V. Sudha
Keywords Low Supply Voltage, SRAM, Read Disturb, Static Voltage, SRAM, Read Disturb, Static Noise Margin, Write Margin
Pages 114-118
Compression of FPGA Bitstreams?A Comparison
Authors M.K. Drisya and Senoj Joseph
Keywords Bitmask-Based Compression, Huffman Coding, Compression Ratio, Field Programmable Gate Array
Pages 119-123
A Distributed Canny Edge Detection and its FPGA Implementation
Authors S. Prasath and S. Umamaheswari
Keywords Canny Edge Detector, Distributed Processing, FPGA
Pages 124-128
Design of High Accuracy Truncated Multiplexer for DCT Applications
Authors Rima Babudas and G. Anusha
Keywords Discrete Cosine Transform(DCT), Distributed Arithmetic(DA) ,Truncation Scheme
Pages 129-132
Static Power Analysis of 32nm CMOS NAND Gate using Active and Standby Leakage Current Reduction Techniques
Authors R. Udaiyakumar, Y. Hamsavarthini and V. Kavitha
Keywords PTM, BSIM, MTCMOS, SCCMOS, FTS, SS, LECTOR
Pages 133- 137
Frequency Synthesis of All Digital Phase Locked Loop Using Sub Micron Technology
Authors S. Saravanakumar and N. Krithika
Keywords All Digital Phase Locked Loops(ADPLL), EDA Tool, CMOS Technology, Frequency Synthesis, Digitally Controlled Oscillator(DCO), Digitally Programmable Delay Element (DPDE).
Pages 138-142
Implementation of Parallel DA Technique for DWT-IDWT on FPGA for Image Compression
Authors K.B. Sowmya, Dr. Savita Sonoli and M. Nagabushanam
Keywords Discrete Wavelet Transform (DWT), Distributive Arithmetic (DA), Look-Up Table (LUT), FIR Filter
Pages 143-148
Digit Serial Finite Field Multiplier Using Normal Basis for Cryptographic Applications
Authors N. Gayathri and P.F. Khaleelur Rahiman
Keywords Finite Field Multiplier, Normal Basis, Digit Serial Architecture, Elliptic Curve Cryptography
Pages 149-151
Built-In Jitter Measurement Circuit Using Multi-Phase Sampler for Clock Generator
Authors S. Pradeepa and Dr.M. Jagadeeswari
Keywords Built-In Jitter Measurement Circuit (BIJM), Time Amplifier (TA), Vernier Ring Oscillator (VRO), Modified Time Amplifier (TA), Multiphase Sampler (MPS), Sense Amplifier Delay Flip-Flop (SA DFF)
Pages 152-155
